The present invention generally relates to a processing system and more particularly to a processing system which exhibits improved efficiency in memory accessing during sequential memory accesses.
Processing systems are well known in the art. Such systems generally include a processor which performs executions on operand data pursuant to operating instructions and a memory for providing the processor with the operating instructions and data. The processor of such a system is also generally arranged to write data to the memory, such as resultants, resulting from the executions performed on operand data.
The reading of operating instructions and data from the memory and the writing of data to the memory are generally referred to as memory accesses by the processor. During a single access, the processor reads or writes a full or partial word of information from the memory. A full word may, for example, be 32 bits wide, and a partial word, 16 bits wide.
The memory, for storing the data and instructions, generally includes a plurality of memory locations with each location having a unique memory location address. In many instances, the memory is formed by a plurality of memory banks with each bank having a plurality of addressable storage locations. The memory banks are generally organized such that each memory location of one bank finds a corresponding memory location in the other banks having the same address except for a one- or two-bit designator which designates the memory bank in which the addressed memory location resides. For example, in a two memory bank system, a memory location of the first bank may have an address N while the corresponding memory location of the second bank may have an address of N+4. The memory addresses may be, for example, 32 bits wide with the addresses differing in the third or A(2) bit s that when the A(2) bit is zero, the first bank is addressed and when the A(2) bit is one, the second bank is addressed. As a further example, in a four memory bank system, a memory location of the first bank may have an address N while the corresponding memory location of the second, third and fourth banks would have addresses N+4, N+8, and N+12, respectively. Here, the A(3) and A(2) bits of the-32-bit address would serve as the designator to determine which bank is being addressed.
In performing memory accesses, the processor generates a memory location address and conveys the same over a multiple-bit address bus to the memory banks. For a read operation, a memory controller provides a ready signal while the memory bank having the memory storage location corresponding to the conveyed address provides the requested data or instruction from that memory location to the processor over a bi-directional, multiple-bit, data/instruction bus. For a write operation, the memory controller provides the ready signal and the processor provides the addressed memory storage location with the data over the data/instruction bus.
The timing between the processor and the memory is generally controlled by a system clock which may be external to the processor or generated by the processor. The system clock provides a series of clock cycles including a high phase and a low phase. The timing control by the system clock may be such that the processor provides addresses, control signals and data during the high phase of the system clock and receives control signals and data or instructions from the memory during the low phase.
Processing systems generally require multiple system clock cycles from the time the processor provides a memory address to when the memory either provides the requested data or instruction word in the case of a read access or to when the memory is ready to receive the data word from the processor in the case of a write access. For example, such a sequence can require two system clock cycles, four system clock cycles, or more than four system clock cycles, depending upon the design of the processing system. While such time periods for memory accesses may be acceptable for single, one word accesses, it would be desirable to speed-up this process when multiple-words of information ar to be conveyed between the processor and memory banks, as, for example, during sequential memory accessing.
The processing system of the present invention provides efficient transfer of multiple words of information between the processor and memory when the processor makes a sequential address memory access request. The present invention is more particularly of advantage when the processor makes a sequential address memory access request wherein the memory banks are interleaved. Interleaving is a process, well known in the art, wherein the address banks are sequentially addressed by a processor.
As will be seen hereinafter, the present invention provides efficient sequential address accessing by permitting the processor to address only a certain one or certain ones of the memory banks. A memory controller sequences the other memory banks in proper order to permit the microprocessor to generate the address of the memory location of the memory banks it is to address early to the end that words of information can be conveyed between the processor and the memory at a rate of one word per system clock cycle.